Trojans in Early Design Steps—An Emerging Threat

Hardware Trojans inserted by malicious foundries during integrated circuit manufacturing have received substantial attention in recent years. In this paper, we focus on a different type of hardware Trojan threats: attacks in the early steps of design process. We show that third-party intellectual property cores and CAD tools constitute realistic attack surfaces and that even system specification can be targeted by adversaries. We discuss the devastating damage potential of such attacks, the applicable countermeasures against them and their deficiencies

Synthesis of Topological Quantum Circuits

Topological quantum computing has recently proven itself to be a very powerful model when considering large- scale, fully error corrected quantum architectures. In addition to its robust nature under hardware errors, it is a software driven method of error corrected computation, with the hardware responsible for only creating a generic quantum resource (the topological lattice). Computation in this scheme is achieved by the geometric manipulation of holes (defects) within the lattice. Interactions between logical qubits (quantum gate operations) are implemented by using particular arrangements of the defects, such as braids and junctions. We demonstrate that junction-based topological quantum gates allow highly regular and structured implementation of large CNOT (controlled-not) gate networks, which ultimately form the basis of the error corrected primitives that must be used for an error corrected algorithm. We present a number of heuristics to optimise the area of the resulting structures and therefore the number of the required hardware resources.Comment: 7 Pages, 10 Figures, 1 Tabl

Software Pauli Tracking for Quantum Computation

The realisation of large-scale quantum computing is no longer simply a hardware question. The rapid development of quantum technology has resulted in dozens of control and programming problems that should be directed towards the classical computer science and engineering community. One such problem is known as Pauli tracking. Methods for implementing quantum algorithms that are compatible with crucial error correction technology utilise extensive quantum teleportation protocols. These protocols are intrinsically probabilistic and result in correction operators that occur as byproducts of teleportation. These byproduct operators do not need to be corrected in the quantum hardware itself. Instead, byproduct operators are tracked through the circuit and output results reinterpreted. This tracking is routinely ignored in quantum information as it is assumed that tracking algorithms will eventually be developed. In this work we help fill this gap and present an algorithm for tracking byproduct operators through a quantum computation. We formulate this work based on quantum gate sets that are compatible with all major forms of quantum error correction and demonstrate the completeness of the algorithm.Comment: 5 Pages, 1 figure, Accepted for Design, Automation and Test In Europe (DATE'2014

Low-power emerging memristive designs towards secure hardware systems for applications in internet of things

Emerging memristive devices offer enormous advantages for applications such as non-volatile memories and in-memory computing (IMC), but there is a rising interest in using memristive technologies for security applications in the era of internet of things (IoT). In this review article, for achieving secure hardware systems in IoT, low-power design techniques based on emerging memristive technology for hardware security primitives/systems are presented. By reviewing the state-of-the-art in three highlighted memristive application areas, i.e. memristive non-volatile memory, memristive reconfigurable logic computing and memristive artificial intelligent computing, their application-level impacts on the novel implementations of secret key generation, crypto functions and machine learning attacks are explored, respectively. For the low-power security applications in IoT, it is essential to understand how to best realize cryptographic circuitry using memristive circuitries, and to assess the implications of memristive crypto implementations on security and to develop novel computing paradigms that will enhance their security. This review article aims to help researchers to explore security solutions, to analyze new possible threats and to develop corresponding protections for the secure hardware systems based on low-cost memristive circuit designs

Optimizing Quantum Algorithms on Bipotent Architectures

Vigorous optimization of quantum gates has led to bipotent quantum architectures, where the optimized gates are available for some qubits but not for others. However, such gate-level improvements limit the application of user-side pulse-level optimizations, which have proven effective for quantum circuits with a high level of regularity, such as the ansatz circuit of the Quantum Approximate Optimization Algorithm (QAOA). In this paper, we investigate the trade-off between hardware-level and algorithm-level improvements on bipotent quantum architectures. Our results for various QAOA instances on two quantum computers offered by IBM indicate that the benefits of pulse-level optimizations currently outweigh the improvements due to vigorously optimized monolithic gates. Furthermore, our data indicate that the fidelity of circuit primitives is not always the best indicator for the overall algorithm performance; also their gate type and schedule duration should be taken into account. This effect is particularly pronounced for QAOA on dense portfolio optimization problems, since their transpilation requires many SWAP gates, for which efficient pulse-level optimization exists. Our findings provide practical guidance on optimal qubit selection on bipotent quantum architectures and suggest the need for improvements of those architectures, ultimately making pulse-level optimization available for all gate types

Multi-Stage Fault Attacks on Block Ciphers

This paper introduces Multi-Stage Fault Attacks, which allow Differential Fault Analysis of block ciphers having independent subkeys. Besides the specification of an algorithm implementing the technique, we show concrete applications to LED-128 and PRINCE and demonstrate that in both cases approximately 3 to 4 fault-injections are enough to reconstruct the full 128-bit key